Hardware Implementation of Random Number Generators

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dc.contributor.author Wijesinghe, W.A.S.
dc.contributor.author Jayananda, M.K.
dc.contributor.author Sonnadara, D.U.J.
dc.date.accessioned 2012-12-19T04:57:30Z
dc.date.available 2012-12-19T04:57:30Z
dc.date.issued 2006
dc.identifier.citation Proceedings of the Technical Sessions, Institute of Physics Sri Lanka, 22 (2006) 25-36
dc.identifier.uri http://archive.cmb.ac.lk:8080/xmlui/handle/70130/3256
dc.description.abstract Random numbers are used in a wide variety of applications. True random number generators are slow and expensive for many applications while pseudo random number generators (RNG) suffice for most applications. Although a majority of random number generators have been implemented in software level, increasing demand exists for hardware implementation due to the advent of faster and high density Field Programmable Gate Arrays (FPGA). FPGAs make it possible to implement complex systems, such as numerical calculations, genetic programs, simulation algorithms etc., at hardware level. This paper discusses in detail the hardware implementation of several RNGs and their characteristics. Somewhat complex Cellular Automata based RNGs show slightly improved performance compared to the simplest Linear Feedback Shift Register RNG.
dc.language.iso en en_US
dc.subject Random numbers
dc.subject FPGA
dc.title Hardware Implementation of Random Number Generators en_US
dc.type Research paper en_US


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