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|Title:||Simulation of Diffusion Limited Aggregation in Field Programmable Gate Arrays|
|Citation:||Journal of National Science Foundation, 38 4 (2010) 213-218|
|Abstract:||This paper presents design considerations and performance in implementation of Diffusion-limited aggregation (DLA) process on a Xilinx Spartan 3 Field Programmable Gate Array (FPGA). The DLA cluster algorithm was implemented as a block RAM and two 32-bit Linear Feedback Shift Register random number generators in hardware. The complete design, written in VHDL and synthesized using Xilinx WebPACK 7.2 was downloaded to the Spartan 3 device for speed measurements. A 300% speed improvement compared to a software based implementation of the same algorithm was observed when the design was tested in a XC3S1000 FPGA operated with a 100 MHz clock.|
|Appears in Collections:||Department of Physics|
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