Please use this identifier to cite or link to this item:
http://archive.cmb.ac.lk:8080/xmlui/handle/70130/235
Title: | Simulation of Diffusion Limited Aggregation in Field Programmable Gate Arrays |
Authors: | Wijesinghe, W.A.S. Jayananda, M.K. Sonnadara, D.U.J. |
Keywords: | Diffusion Field Gate Arrays |
Issue Date: | 2010 |
Citation: | Journal of National Science Foundation, 38 4 (2010) 213-218 |
Abstract: | This paper presents design considerations and performance in implementation of Diffusion-limited aggregation (DLA) process on a Xilinx Spartan 3 Field Programmable Gate Array (FPGA). The DLA cluster algorithm was implemented as a block RAM and two 32-bit Linear Feedback Shift Register random number generators in hardware. The complete design, written in VHDL and synthesized using Xilinx WebPACK 7.2 was downloaded to the Spartan 3 device for speed measurements. A 300% speed improvement compared to a software based implementation of the same algorithm was observed when the design was tested in a XC3S1000 FPGA operated with a 100 MHz clock. |
URI: | http://archive.cmb.ac.lk:8080/xmlui/handle/70130/235 |
Appears in Collections: | Department of Physics |
Files in This Item:
File | Description | Size | Format | |
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Abstract 24.doc | 57.5 kB | Microsoft Word | View/Open |
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